A pipeline doesn't make one instruction faster — it overlaps five of them, so a finished one drops off the end every cycle even though each still crosses five stations. Latency is unchanged; throughput multiplies. Henry Ford's 1913 moving line taught the same lesson in steel.
When an instruction needs a neighbour's result too soon, the line jams and inserts a bubble — a wasted cycle. A forwarding wire routes the value straight back to the ALU before it's ever written to the register file, so most data hazards vanish at zero cost.
The one it can't kill is the load-use stall: a load's value isn't fetched until the end of MEM, the very cycle the next instruction wants it — nothing exists yet to forward. One stall is irreducible; only reordering the code removes it.
You can't forward a control hazard either — a branch is a guess. A 2-bit saturating counter (Yeh & Patt, 1991) keeps a bit of hysteresis, so it shrugs off a loop's single exit and mispredicts once per loop where a 1-bit predictor misses twice.
Something in the simulation stopped unexpectedly — the lesson continues without it. You can move on; nothing you did was wrong.